An analog phase-locked loop (PLL) includes a charge pump that is driven by a phase detector with up and down signals. The charge pump typically includes a PMOS switch transistor that switches on responsive to an assertion of the up signal so that a PMOS current source transistor sources a current through the PMOS switch transistor to charge a control voltage at a drain terminal of the PMOS switch transistor. Such a charge pump will also include an NMOS switch transistor that switches on responsive to an assertion of the down signal so that an NMOS current source transistor sinks a current through the NMOS switch transistor to discharge the control voltage since a drain terminal for the NMOS switch transistor is connected to the drain terminal for the PMOS switch transistor. When the PMOS switch transistor is not switched on because the up signal is not asserted, a drain terminal for the PMOS current source transistor is charged to a power supply voltage. Conversely, when the NMOS switch transistor is not switched on because the down signal is not asserted, a drain terminal for the NMOS current source transistor drain is discharged. These charged drain terminals for the current source transistors then engage in charge sharing with a loop filter for the PLL when their switch transistors are switched on. The resulting charge sharing disturbs the control voltage and lowers the PLL performance.
To mitigate such charge sharing, it is conventional to keep the drain terminal voltages for the current source transistors charged to the control voltage by arranging the switch transistors in parallel with duplicate switch transistors that are driven by a complement of the corresponding up or down signals. It thus doesn't matter whether the up or down signal is asserted since either the original switch transistor or its duplicate will always be on. An operational amplifier (op-amp) maintains the drains of the duplicate PMOS and NMOS switch transistors to equal the control voltage so that the loop filter is not affected by charge sharing. But high-speed operation of a PLL results in a wide swing for the control voltage such that it may range rail to rail (from ground to the power supply voltage). The resulting op-amp must then also be wide swing. In addition, the op-amp must be able to source or sink a relatively large current to adequately support the PLL operation. But conventional op-amps such as a class AB operational amplifier 100 (which may also be denoted as a sense amplifier 100) shown in FIG. 1 have difficultly satisfying such output current and wide swing demands. As is known in the wide-swing sense amplifier arts, sense amplifier 100 includes not only a PMOS differential pair of transistors P1 and P2 but also an NMOS differential pair of transistors M1 and M2. A differential input voltage formed by the difference between an input voltage inp and an input voltage inn drives the two complementary differential pairs of transistors. In particular, input voltage inp drives the gates of transistors P1 and M1 whereas input voltage inn drives the gates of transistors P2 and M2. A current source 105 biases the sources of transistors P1 and P2. Similarly, a current source 125 biases the sources of transistors M1 and M2.
A class AB output stage for sense amplifier 100 is formed by a PMOS output transistor P4 and an NMOS output transistor M4. A biasing network responds to the currents in the differential pairs to drive the gate of output transistor P4 with a pgate drive voltage and to drive the gate of output transistor M4 with an ngate drive voltage. In particular, the biasing network includes a diode-connected PMOS transistor P6 coupled between a power supply node for the power supply voltage VCC and the drain of differential pair transistor M1. The gate (and drain) of diode-connected transistor P6 connects to the gate of a PMOS transistor P5 having its source tied to the power supply node and a drain connected to the drain of differential pair transistor P2. Diode-connected transistor P6 and transistor P5 thus form a current mirror so that transistor P5 conducts a mirrored-version of the current conducted by differential pair transistor M1. An NMOS diode-connected transistor M6 couples between the drain of differential pair transistor P2 and ground. Diode-connected transistor M6 thus conducts a sum current that equals a sum of the currents conducted by differential pair transistors M1 and P2. Diode-connected transistor M6 forms a current mirror with an NMOS transistor M8 having its source tied to ground and a drain tied to an ngate node at the gate of output transistor M4. Transistor M8 will thus sink a mirrored version of the sum current conducted by diode-connected transistor P6 from the ngate node for transistor M4, which causes a discharge of the ngate drive voltage.
The biasing network includes analogous circuitry to source a sum current to the gate of output transistor P4 to charge the pgate drive voltage. In particular, the drain of differential pair transistor P1 couples to ground through an NMOS diode-connected transistor M5 that forms a current mirror with an NMOS transistor M7 having its source tied to ground and a drain tied to the drain of differential pair transistor M2. The drain of differential pair transistor M2 couples to the power supply node through a PMOS diode-connected transistor P7. Diode-connected transistor P7 will thus conduct a sum current equaling the sum of the currents conducted by differential pair transistors P1 and M2. Diode-connected transistor P7 forms a current mirror with a PMOS transistor P8 having its source tied to the power supply node and its drain tied to the pgate node at the gate of output transistor P4. Transistor P8 will thus source a mirrored-version of the sum current conducted by diode-connected transistor P7 into the gate of output transistor P4 to charge the pgate drive voltage.
The wide swing or rail-to-rail performance is given by the complementary differential pairs. For example, as the common mode for input voltages inp and inn rises toward the power supply voltage, the PMOS differential pair of transistors P1 and P2 switch off. The feedback through sense amplifier 100 causes the ngate drive voltage to discharge such that output transistor M4 is switched off. The biasing network also includes a PMOS transistor P3 and an NMOS transistor M3 coupled in parallel between the gates of output transistors P4 and M4. Transistor M3 is biased by a bias voltage nbias such that it switches on as the ngate drive voltage is discharged to also discharge the pgate drive voltage. This discharge of the pgate drive voltage switches on output transistor P4 so that an output voltage (Vout) at the drains of output transistors P4 and M4 may be charged towards the power supply voltage VCC. But due to offsets in the differential pair of transistors M1 and M2, the pgate drive voltage cannot be pulled sufficiently low enough to fully drive output transistor P4 in the deep triode region as the output voltage approaches the power supply voltage VCC. A similar offset in the differential pair of transistors P1 and P2 affects the output voltage when the common mode for input voltages inp and inn is discharged. In that case, differential pair transistors M1 and M2 are switched off. Feedback through sense amplifier 100 then charges the pgate drive voltage towards the power supply voltage. Transistor P3 is biased by a bias voltage pbias such that it switches on to charge the ngate drive voltage ngate as the pgate drive voltage is charged. The output transistor M4 is thus switched on while output transistor P4 is switched off to discharge the output voltage. But again due to an offset voltage between differential pair transistors P1 and P2, the ngate drive voltage cannot be driven sufficiently high enough to fully drive output transistor M4 on in the deep triode region. It is thus conventional to oversize output transistors M4 and P4 so that they can conduct the required amount of currents at these corner conditions. The quiescent current consumption is then increased, which hampers low power operation.
Accordingly, there is a need in the art for wide swing sense amplifiers with reduced power consumption.